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Power Compiler
Synopsys’ Power Compiler™ provides dynamic and leakage
power optimization at RTL and gate-level within Synopsys’
synthesis and physical design flow. At the RTL, during
the design elaboration phase, Power Compiler performs
automatic clock gating to reduce the power consumption.
At the gate level, driven by the designer constraints, it
performs simultaneous optimization for timing, power and
area. Offered within the Galaxy™ Design Platform, Power
Compiler shares the same GUI, commands, constraints and
libraries with Design Compiler® and Physical Compiler®.
Key benefits:
- Dynamic and leakage power optimization at RTL and
gate-level within Synopsys’ synthesis and physical
design flow
- Tapeout-proven by leading semiconductor companies
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