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Physical Compiler
Physical Compiler®, the cornerstone of Synopsys’ physical
synthesis solution and a key component of Synopsys’ Galaxy™
Design Platform, enables register-transfer level (RTL)
designers to deliver the highest-performance circuits in the
shortest time. By unifying synthesis and placement, Physical
Compiler offers designers predictable timing closure from
RTL to placed-gates for their most complex designs. Proven
interfaces to third-party routers allow it to easily plug into an
existing design flow.
Built upon the industry-standard Design Compiler®, Physical
Compiler works seamlessly with Synopsys’ floor planning,
power, datapath, test, routing, and DesignWare® solutions.
Physical Compiler has been widely adopted by the design
community with over a thousand tapeouts attributed to
it. Physical Compiler enables customers to meet their
time to market requirements with significant performance and
productivity gains. All major ASIC vendors have design kit
support for Physical Compiler and are using placement
handoff to quickly close timing on their most complex designs.
Key benefits:
- Delivers best QoR in terms of timing, power, area,
and routability
- Easy to adopt–Similar TCL environment to that of
Design Compiler®, with a rich super set of powerful
commands and easy-to use graphical user interface (GUI)
to get up and running quickly, and get the job done
n Ensures consistent timing, constraints and library throughout
Synopsys tools
- Leverages customer investment
- Plug-and-play solution for third-party place-and-route
flows—industry standard format interfaces ensure
smooth adoption
- Comprehensive ASIC vendor support—users have the
flexibility to choose between ASIC vendors and still
maintain control over their design QoR and CAD tools
- Fast and accurate implementation feasibility analysis –
built-in register transfer level (RTL) Performance
Prototyping (RPP) and quick placement mode help save
time when exploring the effect of physical implementation
on RTL architectural options during early stages of the design
- Very fast runtimes for large (1M to 2M instances) flat chip
designs with distributed physical synthesis (DPS)
- Direct Milkyway™ integration and RC model support enables
a consistent and convergent flow with Astro for faster time
to results
- Global router integration for better timing predictability
on congested designs (required PC Expert option)
- Fast multi-Vth flow with Power Compiler for
leakage optimization
- Opteron 32/64 bit availability starting with v2003.12 for
faster runtimes
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