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Leda
Synopsys’ Leda® is a programmable design and coding guideline
checker that delivers full chip mixed-language (Verilog
and VHDL) and mixed representation (RTL & gate) capabilities
to speed development of complex SoC designs. Leda’s
pre-packaged rules greatly enhance a designer’s ability to
check HDL code for synthesizability, simulatability, testability,
reusability, and RTL/gate signoff.
Key benefits:
- Finds complex bugs, such as those associated with multiple
clock domains using static analysis
n Helps create hardware suitable for simulation, synthesis,
timing, DFT, ERC, and layout
- Enables design reuse with prepackaged guidelines, such as
the Reuse Methodology Manual (RMM), DesignWare®
and STARC
- Isolates hardware design bugs at chip level for multimillion
(>15M) gate designs
- Source code of prepackaged rules can be used as template
for creating custom syntax, semantic and hardware rules
- Enables customization of pre-packaged rules
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