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Formality ESP
FormalityŽ ESP extends the benefits of equivalence checking
by verifying the functional equivalence of Verilog simulation
models versus SPICE netlists for library cells, datapath macros,
and embedded memories. When a difference is found, Formality
ESP produces a set of vectors that highlights the difference.
The circuit designer can then use these vectors to debug their
design to identify the root cause of the mismatch.
Key benefits:
- Ensures high quality verification and eliminates the possibility
of functional errors between models
n Accepts Verilog simulation models written with behavioral or
RTL Verilog
- Eliminates synthesizable subset modeling requirements
- Verifies complex cells that contain self-timed or pre-charge
logic or dynamic circuits
- Quickly identifies the differences between a simulation
model and its corresponding SPICE netlist
- Provides guidance to enable rapid debug of cell mismatches
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