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Formality
FormalityŽ 2004 is an equivalence-checking solution that uses
formal techniques to prove or disprove equivalence between
two versions of the same design. Equivalence checking is a
type of static analysis that verifies large designs both quickly
and completely without the use of test vectors. The high
performance and reduced risk of static analysis has led to
the rapid adoption of equivalence checking within leading
verification flows, making it a must for all competitive design
processes. Formality further reduces time to results by
providing a flow-based graphical interface with advanced
debug capabilities that enable designers to detect and isolate
implementation errors quickly. Formality 2004 features 100%
independent readers, distributed verification, advanced
datapath verification, and automated setup scripting.
Key Benefits:
- Minimizes tape-out risk by providing complete synthesisflow
verification coverage
- Reduces time to market by verifying multimillion-gate designs
in just minutes or hours
- Significantly shortens the traditional equivalence-checking
cycle by reducing setup requirements and providing rapid
error isolation
- Extends hardware investments by providing industry-proven
leading capacity made even faster with distributed verification
- Delivers ASIC, FPGA, mixed language and advanced datapath
capabilities in one product
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