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SiVL Lithography Rule Check
The design verification process must be changed to ensure
that a subwavelength layout will function in silicon. Fortunately,
through the SiVL® (silicon vs. layout) lithography rule-check
(LRC) tool, there is a fast and accurate way to make sure the
silicon produced with subwavelength geometries will function
as intended by the original layout.
SiVL-LRC is an IC design-to-manufacturing tool that verifies
the layout of a subwavelength IC against a simulation of the
silicon it is intended to produce. SiVL-LRC reads in the layout
and simulates lithographic process effects, including optical and
resist effects. SiVL-LRC then compares the results–the
simulated “silicon image”– with the original (intended) layout,
reporting out-of-tolerance regions. SiVL-LRC ensures the
integrity of an IC layout and correctness of its subwavelength
mask design by verifying it against the silicon. This
helps make certain that the ICs produced will function
properly with the performance expected. SiVL-LRC uses a
high-performance, highly accurate simulation engine to verify
that a layout will produce correct silicon.
Key benefits:
- Saves time and money by optimizing OPC structures
based on manufacturability and performance requirements
- Tells you how well the OPC worked without having to wait
for silicon
- Reduces mask complexity and ensures faster turnaround
times and less expensive mask sets
- Enables RET closure
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