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Galaxy™ Design Platform

Synthesis

DC Expert
DC Ultra
DC FPGA
Module Compiler
Physical Compiler

Test Automation

DFT Compiler
DFT Compiler SoCBIST
TetraMAX ATPG

Power Management

Power Compiler
PrimePower

Design Planning

JupiterXT

Physical Implementation

Astro
Astro-Rail
Astro-Xtalk

Extraction

Star-RCXT

Physical Verification

Hercules

Timing and Signal Integrity

PathMill
Prime Time
Prime Time SI
RailMill

Design Database

Milkyway

DesignWare Intellectual Property

DesignWare Library
DesignWare Verification Library
DesignWare Cores
DesignWare Star IP
IP Reuse Tools

Discovery™ Verification Platform

System Analysis and Design

System Studio
SystemC Processor/Bus Models
Saber

Smart RTL Verification

VCS and VCS MX
Magellan
Vera
Leda
DesignWare Verification IP

Functional Equivalence Checking

Formality
Formality ESP
ESP-CV

Mixed-Signal Verification

Cosmos
Discovery AMS
HSPICE
NanoSim

Design for Manufacturing

Mark Synthesis

Proteus
iN-Phase

Mask Data Preparation

CATS

Lithography Verification

SiVL Lithography Rule Check

Mask Qualification

Virtual Stepper
TCAD


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