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ZeBu-ZV Personal EmulatorA New Approach to VerificationEVE has pioneered an entirely new approach to hardware-assisted verification that combines
the best aspects of traditional emulation and rapid prototyping systems into a single, unified
environment for both ASIC/SoC debugging and embedded software validation.
With the high capacity, easy setup and debugging associated with emulation, and the price/
performance of rapid prototyping, ZeBu (for Zero Bugs) is ideal for the system-integration
phase of the design cycle where hardware and embedded software must be verified together.
Hardware design and software development teams can share the same system and design
representation, and can easily collaborate when debugging complex hardware/software interactions.
The net effect is that hardware/software integration takes place much earlier in the
design cycle, thereby reducing silicon respins and accelerating time to market.
ZeBu-ZV has been architected for use by both hardware designers and embedded
software developers.
ZeBu-ZV is a highly affordable, entry-level configuration of the ZeBu family, which offers
capacity of up to 1.5 million ASIC gates, 128Mbit on-board SRAM, and operating speeds up
to 12 MHz. It is ideal for the verification of logic blocks, IP, FPGAs and small ASICs. Built as a
standard PCI card, ZeBu-ZV plugs directly into a desktop PC and integrates with the logic
simulators and synthesis tools that most chip designers use. An in-circuit emulation interface,
ICEpod, connects ZeBu-ZV to a target system and/or hard IP cores via a maximum of
744 I/O pins. In addition, ZeBu-ZV interfaces with popular embedded software debuggers
via a 16 pin interface, called SmartICE, or via a virtual JTAG transactor for added flexibility
and remote usage.
ZeBu-ZV Applications
FASTEST VERIFICATION
Leveraging a wide range of operating
modes, ZeBu supports hardware verification
and embedded software validation throughout
the development cycle.
- Verify and debug ASICs/SoCs, IP cores
With its integrated hardware debugging
resources and high execution speed,
ZeBu is ideal for verifying and debugging
complex functional blocks, IP cores and
full chip designs. Early in the design
cycle ZeBu accelerates simulation in coemulation
with leading HDL simulators
and/or C/C++ code. No changes to existing
HDL testbenches are required, and
ZeBu also supports HVL testbenches such
as Vera™ and e.
- Co-verify hardware and software
Later in the design cycle as the pieces of
the design come together, ZeBu can be
used to validate the entire system by running
the embedded software with either a
synthesizable test bench or in co-emulation
with C++/System C code on the workstation.
ZeBu has been architected for
especially fast co-emulation at the transaction
level, with operating speeds up to
12 MHz.
- Develop and debug embedded software
For software debugging, a JTAG cable or
transactor interface connects standard
embedded software debuggers from
ARM, TI, ARC, Tensilica, etc, to the SoC
under development. In this way ZeBu
can execute software drivers, operating
systems or applications at MHz speed,
while providing full hardware and software
debugging capabilities to both hardware
and software engineers on the same
design representation. For pure software
debugging applications EVE offers a
“replicate” version of ZeBu that is optimized
for the needs of embedded software
developers, at a fraction of the cost
of a full ZeBu system.
ZeBu-ZV is a standard PCI card that
plugs into a PC| Operating Mode | Performance | | Co-emulation with commercial HDL simulator | 5K-100KHz | | Co-emulation with signal-level C/C++/SystemC | 100K-500KHz | | Co-emulation with transaction-level C++/SystemC | 200K-12MhZ | | Test vectors | 100K-500KHz | | Emulation with synthesizable test bench | 1M-12MHz | | Emulation with SW debuggers via JTAG interface | 1M-12MHz |
Key Features for Hardware
Verification
Rapid setup with the ZeBu compiler:
Automated netlist merging & library
management
Automated bus conflict resolution
Automated multi-FPGA clock
management and routing
Automated netlist clustering
Memory generation & pre-defined
memory models
I/O Multi-data-rate handling
Automated system level place & route
Incremental compilation
Fast, parallel compilation on multiple
PCs
Comprehensive hardware debugging
environment, including:
Run-time read/write access of all
registers & memories
Complete internal state capture
without re-compilation
I/O pin & static probe tracing
HW Triggers & built-in logic analyzer
VCD & FSDB generation & waveform
API
Integration with Debussy™ debug
environment
RTL code coverage with VN-Cover™
Integration with popular hardware
design tools:
FPGA & ASIC synthesis: Design
Compiler™, DC FPGA™, SynplifyPro™,
Precision Synthesis™, Xilinx XST™
FPGA place & route: Xilinx ISE™
HDL simulators (Co-emulation):
VCS™, NC-Sim™, ModelSim™
Key Features for HW/SW Co-verification and Embedded
Software Validation
- High speed operation for fast execution of large software programs
- Interfaces with embedded software debuggers for popular cores such as ARM, ARC,
Tensilica and TI
- Enables hardware designers and software developers to collaborate on a common
design representation for quickest resolution of HW/SW integration issues
- Available in reduced-cost “replicate” configuration for embedded software
development
| ZeBu-ZV Product Specifications and System Requirements | | Logic capacity | Up to 1.5M ASIC gates | | On-board SRAM | 128Mbit (8x 16Mbit) | | Operating performance | Up to 12 MHz (see Operating Mode table) | | ICE interface option | 744 I/O pins | | High-speed interface | 16 I/O pins | | Dynamic probe capacity | Run-time access to all registers and memories | | Form factor | Full size PCI card | | PCI Interface | 32bit x 33MHz | | OS | Linux RH 8.0/RH Enterprise/Suse Enterpise 9.0 | | Minimum system requirements | PC Pentium class, 1.5GHz, 512MB | | Dimensions [cm/in] | (10x30x1,4)/(4x11.8x0.55) | | Power Consumption | 12 Watts |
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